The present invention relates to a gate array integrated circuit and, more particularly, to a direct-coupled FET logic (DCFL) gate array using Schottky-barrier FETs.
In the field of Si MOS and bipolar ICs, gate array integrated circuits (ICs) have been developed and commercially available as semi-custom ICs. With such ICs, a master, which constitutes a main part of a device and includes a plurality of basic gates, is fabricated in advance, and by designating the interconnection of the gates in accordance with the specifications of the users, ICs having the desired logical function can be fabricated. In this case, only an interconnection process remains as a manufacturing process after the user specifications are determined, thereby offering a relatively fast production.
A method for realizing high-speed operation and low power dissipation of a gate array IC is to lower the power supply voltage and to minimize a logic swing. In MOS ICs, when the power supply voltage is lowered, the operation speed is decreased. On the other hand, bipolar ICs are difficult to operate at a power supply voltage of about one volt. A circuit utilizing Schottky-barrier FETs (metal-semiconductor field-effect transistors: MESFETs) is known as a circuit which can be operated with a low power supply voltage and a small logic swing. Gate arrays composed of the Schottky-barrier FETs can occupy an independent field as high-speed and low power dissipation gate arrays.
A so-called direct coupled FET logic (DCFL) is known as a basic circuit of a Schottky-barrier FET gate array. This basic circuit uses a normally-on MESFET (i.e., a depletion-mode FET, abbreviated DFET) as a load and a normally-off MESFET (an enhancement-mode FET, abbreviated EFET) as a driver. A resistor may be used as the load in place of a DFET.
In the case of DCFL, the noise margin becomes small because of a small logic swing. Therefore, for example, great care must be taken in designing a master portion in comparison to an Si gate array using a CMOS circuit as a basic cell.
ICs having a gate array fabricated on a GaAs crystal have been reported as the Schottky-barrier FET gate array IC.
In a conventional DCFL GaAs gate array, power supply (VDD) lines and ground (GND) lines coupled to each basic cell are disposed in parallel with each other. (For examples, see the paper by N. Toyoda et al, "500 gates GaAs Gate Array," Proc. 14th Conf. on Solid State Devices, Tokyo, 1982 in Jap. J. Appl. Phys. 22 (1983), Supplement 22-1, pp. 345-348, or the paper by N. Toyoda et al, "Capability of GaAs DCFL for High-Speed Gate Array," Technical Digest, 1982, IEDM, p. 602.)
This is attributed to the following reasons. Generally, the gate width of each FET in a basic cell is made longer than the gate length. For this reason, each basic cell is shaped into a rectangle having a long side along the gate width direction of the FETs. It is desired, therefore, that input and output lines of the basic cell be arranged to extend from a short side of the basic cell, and interconnection tracks for interconnection to the gates of FETs be formed along the short side of the basic cell. Therefore, the basic cells are arrayed such that the long sides of adjacent basic cells are contiguous to each other, thereby forming a cell array (column). On the other hand, the VDD and GND lines must not be arranged to run across the interconnection tracks. This is to avoid manufacturing complexity and to improve manufacturing yield. For this reason, the VDD and GND lines are arranged along the basic cell array.
Such a conventional layout of the VDD and GND lines is no problem in Si-MOS and bipolar ICs with a relatively large logic swing, low-speed ICs, and GaAs gate array ICs having a relatively small number of gates, for example, 500.
However, the present inventors have found that if the conventional layout of the VDD and GND lines as described above is used in the DCFL gate array using Schottky-barrier FETs, a potential difference is produced by a supply current in the VDD and GND lines due to the resistance components thereof, thereby increasing the ground voltage level enough to prevent a correct circuit operation. Particularly, this becomes remarkable when realizing a GaAs gate array having, for example, 1,000 gates or more.
A GaAs gate array having the VDD and GND lines which are arranged perpendicular to each other has been reported (see the paper by A. Rode et al, "A High Yield GaAs Gate Array Technology and Applications," Technical Digest, 1983, GaAs IC Symposium, p. 602). In this gate array, the GND line runs along the basic cell array and the VDD line runs perpendicular to the basic cell array. Particularly, the GND line is realized by airbridge technology to run over the basic cell. The VDD line is realized by a first level interconnection line. Generally, the number of basic cell arrays is smaller than that of the basic cells of each basic cell array. Therefore, in the conventional gate array, the number of the basic cells coupled to one VDD line is smaller than that of the basic cells coupled to one GND line. Since the conventional gate array is fabricated by a complex technique such as airbridge, manufacturing yield is undesirably degraded. If the airbridge technique is not used, a GND line region using a second level interconnection line needs to be arranged adjacent to and parallel to the cell array. This is to prevent the threshold values of FETs from shifting which occurs when the GND line region runs over the FET gates. Further, since signal interconnection lines which run across the cell array must be first level interconnection lines, a region therefor is needed in the cell. In any case, the arrangement of GND line along the column (cell array) results in an increase in the cell area.